1. Field of the Invention:
This invention relates to a method for fabricating capacitors of a dynamic random access memory (DRAM), and more particularly, to a method for fabricating a capacitor of a DRAM by using selective interlayer dielectric formation technology.
2. Description of Related Art:
FIG. 1 shows the circuit of a memory cell that includes a MOS transistor T and a capacitor C within a DRAM. The charging and discharging properties of the capacitor can be used to store data. Generally, a digit in a block of binary information is stored either in a charged capacitor if it is a logic 1 or in an uncharged capacitor if it is logic zero. The source of the MOS transistor T is connected to a corresponding bit line BL, the drain of the MOS transistor T is connected to the storage electrode (or lower electrode) 15 of the capacitor C, and the gate of the MOS transistor T is connected to a corresponding word line. The upper electrode 14 is connected to a fixed voltage source. There is a dielectric layer 12 filling the space between the upper electrode 14 and lower electrodes 15 of the capacitor C.
The capacitor is the major structure used by a memory cell for storing information. If the capacitance of the capacitor is high, the effect caused by noise will be reduced when a piece of information is read, and it will further reduce the refreshing frequency.
Conventionally, a poly spacer etch back technique which utilizes a wet etching process for removing a dummy oxide layer with silicon nitride as the etching stop layer is used for forming cylindrical capacitors. However, it is cracks often occur during the fabrication process due to silicon's high stress.
A conventional method for fabricating cylindrical capacitors of a DRAM is shown in FIGS. 2A through 2E. FIG. 2A shows formation of a field effect transistor on the surface of a semiconductor substrate 200 such as a p-type silicon substrate. The field effect transistor is isolated by field oxide 204; the field effect transistor contains a gate 212, and source/drain 222 and 232. Then, an isolation layer 206, for example, an oxide, and an etching stop layer 216, for example, silicon nitride, are formed in sequence on the substrate 200. A contact hole is formed through the isolation layer and the etching stop layer to expose the source/drain region 222. Source/drain region 222 is designed to couple with transistor. The contact hole is then filled with a conducting material, such as doped polysilicon, to form a conductive plug 242.
In FIG. 2B, a conductive layer 252 and a dummy oxide layer 226 are formed on the top of the etching stop layer 216 in sequence, to define the bottom region of a lower electrode of the desired cylindrical capacitor and to make contact with the conductive plug 242. The conductive layer 252 can be doped polysilicon and the dummy oxide layer 226 can be borophosphosilicate glass (BPSG) or phosphosilicate (PSG).
In FIG. 2C, a conductive layer 262 is formed to cover everything on the top of the substrate 200. The conductive layer can be doped polysilicon.
Next, in FIG. 2D, an anisotropic etching process is performed for forming the conductive spacer 262a, using the etching stop layer 216 as an etch stop. The spacer 262a is the portion of conductive layer 262 on the sides of the dummy oxide layer 226 and in contact with the conductive layer 252. The conductive spacer 262a and conductive layer 252 construe the lower electrode of the cylindrical capacitor 272.
Referring next to FIG. 2E, the dummy oxide layer 226 is removed by a wet etching method. A dielectric layer 236 having a thickness of approximately 10-60 .ANG. is then formed on the exposed surface of the lower electrode of the cylindrical capacitor 272. The dielectric can be silicon oxide, a silicon nitride/silicon oxide (NO) structure, a silicon oxide/silicon nitride/silicon oxide (ONO) structure, or other dielectric materials with high permissivities such as Ta.sub.2 O.sub.5, Pb(Zr,Ti)O.sub.3 (i.e. PZT), or (Ba,Sr)TiO.sub.3 (i.e. BST).
After that, a conductive layer 282 is formed on the top surface of the dielectric layer 236 as the upper electrode of the cylindrical capacitor to complete the capacitor of a DRAM.
However, the conventional method for fabricating cylindrical capacitors of a DRAM has to employ wet a etching process to remove the oxide in the presence of silicon nitride as the etching stop layer. Cracks often occur during the fabrication process due to silicon's high stress; furthermore, the conventional fabrication method is too complicated, and as a result the fabrication cost is not economical.